ASIC DFT Engineer, Silicon
Description For ASIC DFT Engineer, Silicon
Google's Devices & Services team is seeking an ASIC DFT Engineer to join their Silicon team in Bengaluru. This role combines Google's expertise in AI, Software, and Hardware to create innovative user experiences. As a DFT Engineer, you'll work on developing custom silicon solutions that power Google's direct-to-consumer products, collaborating closely with RTL and Physical Designer Engineers.
The position requires expertise in DFT methodologies, including experience with EDA tools, ATPG, BIST, and JTAG. You'll be responsible for working on subsystem level DFT scan and MBIST architecture with multiple voltage and power domains. The role involves writing automation scripts and developing tests for production ATE flow.
This is an excellent opportunity for someone with a background in Electrical or Electronics Engineering who wants to contribute to next-generation hardware experiences at one of the world's leading tech companies. The role offers the chance to work on products used by millions worldwide, pushing the boundaries of hardware innovation.
Google provides a supportive and inclusive work environment, with a strong commitment to diversity and equal opportunity. The company offers comprehensive benefits and focuses on creating a culture of belonging. This role requires English proficiency to facilitate efficient global collaboration.
The ideal candidate will have strong technical skills in DFT methodologies, scripting abilities in Python and TCL, and experience in collaborating with cross-functional teams. You'll be part of Google's mission to organize the world's information and make it universally accessible and useful through cutting-edge hardware solutions.
Responsibilities For ASIC DFT Engineer, Silicon
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains
- Write basic scripts to automate the DFT flow
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow
Requirements For ASIC DFT Engineer, Silicon
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 3 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience architecting/developing DFT flows and methodologies
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
- Excellent scripting skills in languages like Python and TCL
Benefits For ASIC DFT Engineer, Silicon
- Equal employment opportunity
- Accommodations for applicants with special needs
