Design Verification Engineer, ASIC
Description For Design Verification Engineer, ASIC
Google is seeking a Design Verification Engineer to join their ASIC team in Bengaluru. This role is part of Google's initiative to develop custom silicon solutions that power their direct-to-consumer products. The position combines hardware engineering with software development, focusing on verification of complex digital systems.
The ideal candidate will have strong experience in digital logic verification, particularly with SystemVerilog and UVM. They will be responsible for ensuring the functionality and performance of next-generation infrastructure IPs and interconnects. This involves creating sophisticated verification environments, developing cross-language tools, and working closely with design engineers to deliver high-quality silicon products.
This is an excellent opportunity for someone with both hardware and software expertise who wants to impact millions of users through Google's hardware products. The role offers the chance to work with cutting-edge technology and be part of Google's mission to create radically helpful experiences through the combination of AI, software, and hardware.
The position requires a blend of technical skills including RTL verification, programming in various languages, and understanding of modern hardware protocols. You'll be working in a collaborative environment, interfacing with different engineering teams to ensure the delivery of functionally correct systems.
As part of Google's hardware team, you'll contribute to the innovation behind products used worldwide, helping to shape the next generation of hardware experiences. The role offers the opportunity to work on projects that push the boundaries of performance, efficiency, and integration in custom silicon solutions.
Responsibilities For Design Verification Engineer, ASIC
- Plan and execute the verification of the next generation configurable Infrastructure Intellectual Property (IPs), interconnects and memory subsystems
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Develop cross language tools and verification methodologies
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct blocks and subsystems
Requirements For Design Verification Engineer, ASIC
- Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience
- 5 years of experience in coding, developing test methodologies, writing test plans, creating test cases, and debugging
- Experience verifying digital logic at RTL level either using SystemVerilog, C, C++
- Master's degree in Electrical Engineering or Computer Science or equivalent practical experience (preferred)
- Experience with Interconnect Protocols such as AHB, AXI, ACE, CHI, CCIX, CXL (preferred)
- Experience with performance verification of SOC, Pre-Silicon analysis and post-Silicon correlation (preferred)
