Junior Design Verification Engineer, Networking, Google Cloud
Description For Junior Design Verification Engineer, Networking, Google Cloud
Google Cloud is seeking a Junior Design Verification Engineer to join their Networking team. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for designing and implementing hardware, software, and infrastructure for Google services and Cloud platform. As a Design Verification Engineer, you'll work on verification components, constrained-random testing, and system testing for server chip designs. You'll collaborate with design and verification engineers, handling the full verification lifecycle from planning to coverage closure.
The position requires expertise in digital logic verification using SystemVerilog or Specman/E, and you'll be working on cutting-edge hardware solutions that power Google's direct-to-consumer products. The role combines technical skills in verification methodologies with collaborative teamwork to ensure the functionality and reliability of complex digital designs.
This is an excellent opportunity for someone early in their career to work on advanced hardware projects at scale, contributing to products used by millions worldwide. The position offers the chance to work with industry-leading tools and methodologies while being part of a team that pushes the boundaries of hardware innovation.
The role is based in either Tel Aviv or Haifa, Israel, and requires strong technical fundamentals in verification engineering. You'll be part of Google's broader mission to shape the future of hyperscale computing, working on projects that impact both Google's internal services and Cloud customers globally.
Responsibilities For Junior Design Verification Engineer, Networking, Google Cloud
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Apply close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Junior Design Verification Engineer, Networking, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs
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