Machine Learning Hardware Architect, Accelerator
Description For Machine Learning Hardware Architect, Accelerator
Google is seeking a Machine Learning Hardware Architect to join their team developing custom silicon solutions for direct-to-consumer products. This role combines advanced machine learning with hardware architecture, focusing on the development of Tensor Processing Units (TPUs) and machine learning accelerators for System on Chip (SoC) implementations.
The position requires deep expertise in computer architecture, particularly in designing and optimizing hardware for machine learning workloads. You'll be responsible for developing next-generation TPU architectures that push the boundaries of performance, power efficiency, and area optimization. This involves close collaboration with Google's research teams, silicon product management, and various hardware design teams across global sites.
As a Machine Learning Hardware Architect, you'll play a crucial role in defining product roadmaps for ML accelerator capabilities in various Google devices. The work involves balancing complex technical requirements including power consumption, performance metrics, and area efficiency at the SoC level, particularly for multimedia and AI applications.
The role offers an opportunity to work at the cutting edge of machine learning hardware development, contributing to products used by millions of people worldwide. You'll be part of Google's broader mission to organize the world's information and make it universally accessible, working specifically on the hardware innovations that enable next-generation AI capabilities.
The position comes with competitive compensation including a base salary range of $156,000-$229,000, plus bonus, equity, and comprehensive benefits. Google offers a collaborative environment where you'll work with top talent across research, design, and development teams, pushing the boundaries of what's possible in machine learning hardware.
This is an ideal role for someone with strong technical expertise in silicon architecture and machine learning, who wants to make a significant impact on the future of AI hardware acceleration. The position requires both deep technical knowledge and the ability to work effectively across multiple teams to deliver complex hardware solutions that meet Google's high standards for performance and efficiency.
Responsibilities For Machine Learning Hardware Architect, Accelerator
- Develop TPU (Tensor Processing Unit) architecture for next-generation tensor SOC
- Define the product roadmap for machine learning accelerator capabilities on System on a Chip (SoCs)
- Drive hardware Internet Protocol (IP) architecture specifications into design implementation for SoCs
- Align with SoC architects and system architects to address dynamic power, performance, and area requirements
- Define and deliver hardware IP architecture specifications that meet power, performance, area and image quality goals
Requirements For Machine Learning Hardware Architect, Accelerator
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience of silicon core architectural domains, including computer architecture, TPU or parallel processor architecture (VPU/DSP), micro-architecture and silicon design
- Experience in architecting and designing machine learning hardware IP in SoCs for machine learning networks
- Experience in algorithms for machine learning accelerators and compute cores
- Experience in micro architecture, power and performance optimization
- Experience in interconnect/fabric, caching and security architectures
Benefits For Machine Learning Hardware Architect, Accelerator
- Bonus
- Equity
- Benefits package
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