ML Hardware Architecture Modeling and Co-design Engineer
Description For ML Hardware Architecture Modeling and Co-design Engineer
Google is seeking an ML Hardware Architecture Modeling and Co-design Engineer to shape the future of AI/ML hardware acceleration through TPU (Tensor Processing Unit) technology. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and Cloud platform.
The position involves working with hardware and software architects to model, analyze, and define next-generation TPUs. You'll be contributing to cutting-edge TPU technology that powers Google's most demanding AI/ML applications, including services used by billions of people worldwide. The role combines elements of machine learning, computer architecture, and hardware design, requiring expertise in performance analysis and software development.
Key responsibilities include conducting ML workload characterization, performing performance and power analyses, developing architectural models, and collaborating across teams for effective hardware/software co-design. You'll be instrumental in proposing capabilities for next-generation TPUs and contributing to chip specifications.
The position offers competitive compensation ($132,000-$189,000 base salary) plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone with a strong background in computer architecture and software development who wants to work at the intersection of hardware and machine learning, contributing to technology that powers some of the world's most widely-used AI applications.
Google provides an inclusive work environment and is committed to equal opportunity employment. The role is based in Sunnyvale, CA, and requires strong technical skills, particularly in C++ or Python development, along with experience in computer architecture performance analysis. The position offers the chance to work with cutting-edge technology while collaborating with leading experts in the field of AI hardware acceleration.
Responsibilities For ML Hardware Architecture Modeling and Co-design Engineer
- Machine Learning workload characterization, benchmarking, and hardware-software co-design
- Conduct performance and power analyses and quantitatively evaluate proposals
- Develop architectural and micro architectural models to enable quantitative analysis
- Collaborate with partners in hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign
- Propose capabilities and next-generation TPUs and chip roadmap, and contribute to TPU chip specs
Requirements For ML Hardware Architecture Modeling and Co-design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience in computer architecture performance analysis, or a PhD degree in lieu of industry experience
- Experience in developing software systems in C++ or Python
Benefits For ML Hardware Architecture Modeling and Co-design Engineer
- Medical Insurance
- Equity
- 401k
