Join Google's gChips team as a Multimedia Core IP RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on designing interconnect IP for Pixel System on Chip (SoCs), combining the best of Google AI, Software, and Hardware to create innovative experiences.
As part of the team, you'll collaborate with architects, software engineers, and verification specialists to deliver high-quality Register-Transfer Level (RTL) designs. Your work will involve solving complex technical challenges in micro-architecture, RTL implementation, and low power design methodology, while carefully balancing performance, power, and area considerations.
The gChips team is responsible for developing SoCs and other mixed signal, logic, and sensor ICs that provide differentiated user experiences in Google Hardware products. Working closely with product teams, you'll help shape the future of silicon requirements looking 2-4 years ahead, ensuring Google stays at the cutting edge of chip technologies and standards.
This position requires expertise in RTL coding, computer architecture, and ASIC design methodologies. You'll work on exciting projects involving Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, and other multimedia IPs such as Display or Video Codecs. The role offers the opportunity to contribute to products used by millions worldwide while working with a global team of experts.
Google offers a collaborative environment where you'll push boundaries in hardware development, optimize performance and power efficiency, and help create the next generation of innovative hardware experiences. If you're passionate about silicon design and want to make a significant impact on Google's hardware products, this role provides an excellent opportunity to work with cutting-edge technology and talented professionals.