RTL Design Engineer, Multimedia and Machine Learning, Silicon
Description For RTL Design Engineer, Multimedia and Machine Learning, Silicon
Google is seeking an RTL Design Engineer specializing in Multimedia and Machine Learning for their Silicon team in Bengaluru, India. This mid-level position requires a minimum of 3 years of experience in digital logic design and RTL concepts.
The role involves developing RTL designs for camera and machine learning applications, including RTL coding, lint cleanup, SoC IP release flows, architecture and micro-architecture design, and power, performance, and area (PPA) optimizations. The engineer will also collaborate on test planning and conduct coverage reviews to ensure high-quality Core IP deliveries.
Key responsibilities include:
- Performing Verilog/SystemVerilog RTL coding and debugging
- Conducting RTL verification using industry-standard methodologies
- Developing RTL implementations meeting power, performance, and area goals
- Participating in synthesis, timing/power closure, and FPGA/silicon bring-up
- Creating automation tools and scripts
The ideal candidate should have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with experience in logic synthesis techniques, low-power design, and scripting languages like Perl or Python.
Google's mission is to organize the world's information and make it universally accessible and useful. This role contributes to the development of custom silicon solutions that power Google's direct-to-consumer products, pushing boundaries and shaping the next generation of hardware experiences.
The company offers an inclusive work environment and is committed to equal opportunity employment, regardless of background or personal characteristics. They also provide accommodations for applicants with special needs upon request.
Responsibilities For RTL Design Engineer, Multimedia and Machine Learning, Silicon
- Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks
- Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis
- Develop RTL implementations that meet engaged power, performance and area goals
- Participate in synthesis, timing/power closure and FPGA/silicon bring-up
- Create tools/scripts to automate tasks and track progress
Requirements For RTL Design Engineer, Multimedia and Machine Learning, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques
- Experience with a scripting language such as Perl or Python
