Senior Register-Transfer Level Design Engineer, Core IP, Silicon
Description For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
Google's Devices & Services team is seeking a Senior Register-Transfer Level Design Engineer to join their Core IP Silicon team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position combines hardware engineering with RTL design, requiring expertise in ASIC design methodologies and System Verilog/Verilog coding.
The ideal candidate will have 10+ years of RTL design experience and will be responsible for microarchitecture definition, RTL implementation, and system integration. They will work on cutting-edge projects that directly impact Google's hardware experiences, focusing on performance, efficiency, and integration.
This role offers the opportunity to work with Google's advanced AI, Software, and Hardware teams, contributing to products that are used by millions worldwide. The position involves collaboration with multi-disciplinary teams across different locations, working on everything from initial design to silicon bring-up.
Key responsibilities include developing RTL implementations, performing various technical checks and simulations, and participating in verification processes. The role requires both technical expertise and the ability to work effectively in a team environment, making it an excellent opportunity for experienced hardware engineers looking to make an impact at scale.
The position is based in Bengaluru and is part of Google's broader mission to organize the world's information and make it universally accessible and useful. This role offers the chance to work on next-generation hardware experiences while being part of a company known for its innovative technology and global impact.
Responsibilities For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration
- Define and develop Register-Transfer Level (RTL) implementations that meet engaged power, performance and area goals
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
- Create tools/scripts to automate tasks and track progress
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning
Requirements For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 10 years of work experience in RTL design
- Experience with ASIC design methodologies for clock domain checks and reset checks
- Experience in RTL coding using System Verilog/Verilog
