Senior RTL Design Engineer, Core IP, Silicon
Description For Senior RTL Design Engineer, Core IP, Silicon
Google is seeking a Senior RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering expertise with Google's mission to organize world information and make it universally accessible. The position requires deep technical knowledge in RTL design, ASIC methodologies, and system architecture.
The ideal candidate will have extensive experience in RTL design with System Verilog/Verilog, along with strong understanding of power, performance, and area optimization. They will work on cutting-edge hardware designs that directly impact millions of users worldwide through Google's consumer products. The role involves both technical leadership and hands-on development, requiring collaboration with multi-disciplinary teams across different locations.
Key responsibilities include microarchitecture definition, RTL implementation, debugging, and verification. The engineer will be involved in the complete development cycle from design to silicon bring-up. This is an opportunity to work on innovative hardware solutions at one of the world's leading technology companies, with access to state-of-the-art tools and technologies.
The position offers the chance to work on challenging technical problems while contributing to products that have global impact. Google's commitment to innovation in hardware, combined with their focus on user experience, makes this an exciting opportunity for experienced RTL designers looking to push the boundaries of hardware development.
Responsibilities For Senior RTL Design Engineer, Core IP, Silicon
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration
- Define and develop RTL implementations that meet engaged power, performance and area goals
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
- Create tools/scripts to automate tasks and track progress
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning
Requirements For Senior RTL Design Engineer, Core IP, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 10 years of work experience in RTL design
- Experience with ASIC design methodologies for clock domain checks and reset checks
- Experience in RTL coding using System Verilog/Verilog
