Senior SoC and IP Design Engineer, Google Cloud
Description For Senior SoC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative team as a Senior SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced ASIC design with cutting-edge cloud technology, offering an opportunity to impact products used by millions worldwide.
You'll be part of the ML, Systems, and Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and Google Cloud. The position requires expertise in digital logic design, RTL development, and SOC architecture, where you'll contribute to everything from initial architecture to production implementation.
Your responsibilities will span from defining SoC-level design documents to performing detailed RTL development and participating in silicon bring-up. You'll work with various teams, including architecture, software, verification, power, and timing, to develop optimal design solutions balancing performance, power, and area requirements.
The role offers the chance to work on hyperscale computing solutions and contribute to Google Cloud's Vertex AI platform. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of what's possible in custom silicon design.
This position is ideal for someone with strong technical skills in ASIC design who wants to work on large-scale, impactful projects in a collaborative environment. You'll have the opportunity to shape the future of Google's hardware infrastructure while working with some of the industry's most advanced technology and talented engineers.
Responsibilities For Senior SoC and IP Design Engineer, Google Cloud
- Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Participate in architecture feedback
Requirements For Senior SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience in logic design
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with design sign off and quality tools (e.g., Lint, CDC, etc.)
- Experience with SOC architecture
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