Senior SOC RTL Design Engineer, Google Cloud
Description For Senior SOC RTL Design Engineer, Google Cloud
Join Google Cloud's innovative hardware team as a Senior SOC RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's next-generation products. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on critical hardware infrastructure that supports Google's global services and Cloud platform. This role combines deep technical expertise in digital logic design with the opportunity to shape the future of hyperscale computing.
You'll be responsible for defining and implementing SOC/block level designs, working with cutting-edge RTL development, and ensuring optimal performance through synthesis and timing closure. The position requires strong skills in Verilog/SystemVerilog and experience with PCIe protocols. You'll collaborate with multi-disciplinary teams across different locations to deliver robust silicon solutions.
This is an excellent opportunity for experienced RTL designers who want to impact billions of users through Google's infrastructure. You'll work with state-of-the-art technology in areas like machine learning hardware, TPUs, and enterprise-scale systems. The role offers the chance to work on complex technical challenges while contributing to Google Cloud's mission of shaping the future of hyperscale computing.
The position is based in either Tel Aviv or Haifa, Israel, offering the chance to work with world-class engineers in Google's renowned hardware division. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of what's possible in custom silicon design.
Responsibilities For Senior SOC RTL Design Engineer, Google Cloud
- Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with PCIe (PCI)
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