Senior SOC RTL Design Engineer, Google Cloud
Job Description
Join Google Cloud's innovative team as a Senior SOC RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on hardware and systems infrastructure that supports all Google services and Cloud operations. This role combines deep technical expertise in digital logic design, RTL development, and system architecture with the opportunity to impact billions of users worldwide.
You'll be responsible for defining SOC/block level designs, implementing RTL solutions, and ensuring optimal performance through synthesis and verification. The position requires strong skills in Verilog/SystemVerilog, experience with PCIe protocols, and expertise in logic synthesis techniques. You'll collaborate with multi-disciplinary teams across different locations to drive innovation in hardware development.
The role offers the chance to work on cutting-edge technology in a company that prioritizes security, efficiency, and reliability. You'll be part of shaping the future of hyperscale computing and contributing to Google Cloud's Vertex AI platform. This position is perfect for experienced engineers who want to make a significant impact on next-generation hardware experiences while working with state-of-the-art technology and talented colleagues.
Working at Google means joining a company committed to innovation, technical excellence, and creating products that serve billions of users. You'll have access to world-class resources and the opportunity to work on projects that push the boundaries of what's possible in hardware design and system architecture.
Responsibilities For Senior SOC RTL Design Engineer, Google Cloud
- Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with PCIe (PCI)
