Signoff and Design Methodology Engineer, Silicon
Description For Signoff and Design Methodology Engineer, Silicon
Join Google's innovative hardware team as a Signoff and Design Methodology Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced technical expertise in silicon design with the opportunity to impact products used by millions worldwide. You'll be working with state-of-the-art technology, focusing on mobile System on Chip (SoC) design and optimization.
The position requires deep expertise in static timing analysis, synthesis, and physical design automation. You'll be responsible for driving sign-off timing methodologies, analyzing power performance area trade-offs, and working on subsystem prototyping to deliver optimized solutions. Collaboration is key, as you'll work closely with cross-functional teams including architecture, IP, design, power, and sign-off methodology teams.
Google's commitment to innovation in AI, Software, and Hardware makes this an exciting opportunity for someone passionate about pushing the boundaries of silicon design. You'll be part of a team that researches, designs, and develops new technologies to make computing faster, more seamless, and more powerful. The role offers the chance to work with cutting-edge tools and methodologies while contributing to products that make a real difference in people's lives.
The ideal candidate will bring strong technical skills in physical design tool automation, timing constraints, parasitic extraction, and RTL languages. You'll need to be comfortable with complex analysis and optimization, working with foundries, and driving improvements in convergence and yield. This is an opportunity to shape the future of Google's hardware experiences while working with some of the industry's best minds in silicon design.
Responsibilities For Signoff and Design Methodology Engineer, Silicon
- Drive the sign-off timing methodologies for mobile System on a chip (SoCs) to push Power Performance Area (PPA) and yield
- Analyze power performance area trade-offs across different methodologies and technologies
- Work on prototyping of subsystems to deliver optimized PPA recipes
- Work with cross-functional architecture, Internet Protocols (IPs), design, power and sign-off methodology teams
- Work with foundry to refine signoff methodology to improve convergence and yield
Requirements For Signoff and Design Methodology Engineer, Silicon
- Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience
- 5 years of experience with static timing analysis, synthesis, physical design & automation
- Experience in physical design tool automation such as synthesis, P&R and sign-off tools
- Experience in extraction of design parameters, Quality of Results metrics, and analyzing data trends
- Knowledge of timing constraints, convergence and signoff
- Knowledge of parasitic extraction tools and flow
- Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog)
- Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies
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