Silicon SoC RTL Design/Integration Engineer
Description For Silicon SoC RTL Design/Integration Engineer
Google Cloud is seeking a Silicon SoC RTL Design/Integration Engineer to join their Hardware Testing Engineering team. This role is crucial in developing and maintaining Google's custom-designed machines that power one of the world's largest computing infrastructures.
As a member of the Digital Design team, you'll be instrumental in crafting architecture for current and future ASIC projects, focusing on networking solutions. You'll collaborate closely with verification and validation teams to ensure proper feature testing, while working with Google product teams to align microarchitecture designs with their objectives.
The position requires expertise in ASIC development, networking protocols, and design verification. You'll be working with cutting-edge technology, designing test equipment for prototypes, and developing protocols that scale across Google's global infrastructure. The role offers an opportunity to work on high-impact projects that directly influence Google's hardware infrastructure.
Key responsibilities include defining microarchitecture for Subsystems/SoCs, managing current and future ASIC generations, and coordinating with various teams including Physical Design, Verification, Manufacturing, and Product teams. You'll be part of Google's Technical Infrastructure team, which is fundamental in keeping Google's vast network running efficiently and ensuring optimal user experience.
This is an excellent opportunity for someone passionate about hardware engineering, particularly in ASIC design and system architecture, who wants to make a significant impact on Google's infrastructure. You'll be working in an environment that encourages innovation and collaboration, with access to some of the most advanced computing systems in the world.
Responsibilities For Silicon SoC RTL Design/Integration Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Manage the architecture and microarchitecture of current and future generations of ASIC
- Work closely with Physical Design teams to ensure success. Consolidate demands from Verification, Manufacturing and Product teams
- Help drive internal and external users to vet architecture ideas
Requirements For Silicon SoC RTL Design/Integration Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
- Experience in networking, including working with Ethernet, TCP/IP, buffering, queueing, and scheduling
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
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