Silicon Subsystems RTL Design Engineer, Google Cloud
Description For Silicon Subsystems RTL Design Engineer, Google Cloud
Join Google Cloud's innovative team as a Silicon Subsystems RTL Design Engineer, where you'll shape the future of AI/ML hardware acceleration through TPU (Tensor Processing Unit) technology. This role offers the opportunity to drive cutting-edge developments that power Google's most demanding AI/ML applications. You'll be working on custom silicon solutions that are integral to Google's TPU infrastructure, contributing to products used by millions worldwide.
As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll collaborate with cross-functional teams including architecture, verification, power and performance, and physical design experts. Your focus will be on developing ASICs that accelerate and improve data center traffic, solving complex technical problems through innovative micro-architecture and practical logic solutions.
The position requires expertise in ASIC development, design verification, and subsystem architecture. You'll be evaluating design options considering complexity, performance, power, and area constraints. The role combines hands-on technical work with strategic thinking, as you'll be responsible for driving power, performance, and area improvements for your domains.
This is an excellent opportunity for experienced engineers who want to work at the forefront of AI hardware development, contributing to Google's global infrastructure that supports services like Search, YouTube, and Google Cloud. The role offers the chance to work on hyperscale computing solutions and be part of the team developing Vertex AI, Google Cloud's leading AI platform for enterprise customers.
Responsibilities For Silicon Subsystems RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of subsystems in the data center domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Perform Quality check flows like Lint, CDC, RDC, VCLP
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area improvements for the domains owned
Requirements For Silicon Subsystems RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of subsystems
