Taro Logo

SoC Design Verification Engineer, AI Accelerators

Google is a global technology company that specializes in internet-related services and products, including search, cloud computing, software, and hardware.
$127,000 - $187,000
Backend
Mid-Level Software Engineer
In-Person
4+ years of experience
This job posting may no longer be active. You may be interested in these related jobs instead:

Description For SoC Design Verification Engineer, AI Accelerators

As a SoC Design Verification Engineer at Google, you'll be part of a diverse team developing custom silicon solutions for Google's direct-to-consumer products. You'll work on ASICs used to accelerate computation in data centers, with responsibilities including project definition, design verification, and silicon bringup. You'll participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The role involves planning the verification of complex digital design blocks, creating constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), and debugging tests with design engineers. You'll also be responsible for identifying and writing coverage measures for stimulus and corner-cases, and closing coverage measures to show progress towards tape-out.

This position is part of Google's Technical Infrastructure team, which builds and maintains the architecture behind Google's product portfolio. The team ensures networks are up and running, providing users with the best and fastest experience possible.

Google offers a competitive compensation package, including bonus, equity, and benefits. The company is committed to diversity, equity, and inclusion, providing equal employment opportunities to all candidates.

Last updated a year ago

Responsibilities For SoC Design Verification Engineer, AI Accelerators

  • Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
  • Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver correct design blocks
  • Close coverage measures to identify verification holes and to show progress towards tape-out

Requirements For SoC Design Verification Engineer, AI Accelerators

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • Experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
  • Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage)

Benefits For SoC Design Verification Engineer, AI Accelerators

Equity
  • Bonus
  • Equity
  • Comprehensive benefits package