Physical Verification Application Engineer

Intel is seeking a Physical Verification Application Engineer to join their Aerospace, Defense and Government (ADG) division within Intel Foundry Services. This role is part of Intel's IDM 2.0 strategy, establishing a world-class foundry business serving customers globally. The position focuses on providing technical support for layout verification and parasitic extraction, working with both internal teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors.

The role requires expertise in advanced CMOS processes, layout verification tools, and scripting languages. The ideal candidate will be self-driven, analytical, and possess strong communication skills. This position offers an opportunity to work on cutting-edge semiconductor technology while supporting Intel's mission to be a major provider of US and European-based foundry capacity.

The compensation package is highly competitive, ranging from $169,820 to $239,750 annually, complemented by comprehensive benefits including stock options, bonuses, health coverage, and retirement benefits. The position offers a hybrid work model, allowing flexibility between on-site and remote work.

Key responsibilities include collaborating on physical and layout design rules, creating technical documentation, delivering training, and ensuring successful customer design tape-outs. The role requires US citizenship and the ability to obtain a US Government Security Clearance, making it ideal for professionals interested in working at the intersection of advanced semiconductor technology and government/defense applications.

This is an excellent opportunity for experienced professionals looking to contribute to Intel's foundry services expansion while working with advanced technologies and diverse stakeholders in a dynamic, fast-paced environment.