Physical Verification Application Engineer

Intel is seeking a Physical Verification Application Engineer to join their Aerospace, Defense and Government (ADG) division within Intel Foundry Services. This role is part of Intel's IDM 2.0 strategy, establishing a world-class foundry business serving customers globally. The position focuses on providing technical support for layout verification and parasitic extraction, working with both internal teams and external stakeholders.

The ideal candidate will be responsible for collaborating across Intel's ecosystem, including foundry customers' design teams, IP providers, and EDA vendors. They will work on physical and layout design rules, assist with issue resolution, and create technical documentation and training materials. This role requires a strong background in advanced CMOS processes and extensive experience with layout verification tools.

This is an excellent opportunity for experienced engineers who want to work at the forefront of semiconductor technology. The position offers competitive compensation, including a salary range of $169,820 to $239,750, plus comprehensive benefits including stock options, bonuses, and health coverage. The role supports Intel's mission to transform the global semiconductor industry through cutting-edge silicon process and packaging technology leadership.

The position requires US citizenship and the ability to obtain a US Government Security Clearance, indicating its strategic importance. Working in a hybrid model, you'll have the flexibility to split time between on-site and off-site work. This role is perfect for someone who combines technical expertise with strong communication skills and a collaborative mindset.

Join Intel's team and be part of their mission to advance semiconductor technology while working with cutting-edge tools and processes in a dynamic, fast-paced environment.