ASIC Engineer, Design Verification
Job Description
Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization, focusing on building IP and System On Chip (SoC) solutions for data center applications. This role offers an opportunity to work with industry leaders in developing innovative ASIC solutions for Meta's data center infrastructure.
The position involves comprehensive verification responsibilities, from test planning to UVM-based testbench development and verification closure. You'll be working with cutting-edge technologies, employing traditional simulation methods alongside Formal and Emulation approaches to ensure bug-free design implementation. The role demands extensive collaboration with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams to achieve first-pass silicon success.
As an ASIC Design Verification Engineer, you'll be instrumental in defining and implementing verification strategies for IP and SoC levels, developing functional tests, and driving verification to closure based on established metrics. The position requires deep expertise in SystemVerilog/UVM methodology, with a particular focus on AI/ML inference/training ASIC design verification.
Meta offers a competitive compensation package ranging from $212,000 to $291,000 annually, plus bonus, equity, and comprehensive benefits. The role is based in either Sunnyvale or Menlo Park, California, providing an opportunity to work at one of the world's leading technology companies. The position requires 12+ years of relevant experience and offers the chance to work on cutting-edge hardware solutions that power Meta's vast data center infrastructure.
This role is perfect for someone who thrives in a collaborative environment, has a strong background in ASIC design verification, and is passionate about developing next-generation hardware solutions for large-scale data center applications. Join Meta's hardware team and be part of building the infrastructure that powers billions of connections worldwide.
Responsibilities For ASIC Engineer, Design Verification
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
- Develop and drive continuous Design Verification improvements using the latest verification methodologies
Requirements For ASIC Engineer, Design Verification
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Track record of 'first-pass success' in ASIC development cycles
- 12+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
- 12+ years experience in IP/sub-system and/or SoC level verification
- 3+ years experience leading AI/ML inference/training ASIC design verification
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For ASIC Engineer, Design Verification
- Medical Insurance
- Dental Insurance
- Vision Insurance
- Equity
