Physical Design Power Optimization Engineer
Description For Physical Design Power Optimization Engineer
NVIDIA, the world leader in accelerated computing, is seeking a Physical Design Power Optimization Engineer to join their Networking Silicon Power engineering team. This role is crucial in developing industry-leading high-speed communication devices that deliver maximum throughput, minimal latency, and optimal power efficiency. As part of NVIDIA's innovative team, you'll work on groundbreaking chip designs in a professional, growth-oriented environment.
The position involves sophisticated power optimization work across all aspects of physical design chip development, from RTL to GDS. You'll be responsible for synthesis, power and clock distribution, place and route, timing closure, and implementing power and noise fixes. This role offers an excellent opportunity for early-career engineers to work with cutting-edge technology and make significant contributions to NVIDIA's chip development process.
The ideal candidate should have a strong educational background in Electrical or Computer Engineering, with some familiarity with physical design EDA tools like Synopsys and Cadence. While the role is entry-level (0-2 years of experience), it offers extensive exposure to advanced chip design methodologies and tools. You'll be working in a collaborative environment that values problem-solving abilities and strong interpersonal skills.
Join NVIDIA's best-in-class physical design team and be part of a company that's transforming industries through AI and accelerated computing. This position offers the chance to work on meaningful projects while developing expertise in chip design and power optimization.
Responsibilities For Physical Design Power Optimization Engineer
- Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints
- Optimization involves all aspects of physical design chip development (RTL2GDS)
- Synthesis, power and clock distribution
- Place and route, timing closure
- Power and noise fixes
Requirements For Physical Design Power Optimization Engineer
- B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering
- 0-2 years of experience in physical design and/or BE power optimization aspects
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage
- FE design experience is an advantage
- Excellent problem-solving, partnership, and interpersonal skills
