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Physical Design Signoff CAD Engineer

NVIDIA is the world leader in accelerated computing, pioneering solutions in AI and digital twins that transform industries.
Backend
Entry-Level Software Engineer
Hybrid
5,000+ Employees
1+ year of experience
AI · Enterprise SaaS

Description For Physical Design Signoff CAD Engineer

NVIDIA is seeking an exceptional Physical Design CAD Engineer to join their Networking Silicon engineering team. This role is crucial in developing industry-leading high-speed communication devices that deliver maximum throughput and minimal latency. As part of NVIDIA's innovative team, you'll work on groundbreaking chip designs in a professional, growth-oriented environment.

The position involves developing sophisticated physical design workflows, focusing on Static Timing Analysis (STA), Logic equivalence, and Power Integrity methodologies for networking chips and SOCs. You'll collaborate closely with block owners and Chip STA engineers to ensure high-quality deliverables and timely project completion. The role requires creative problem-solving skills to address cutting-edge physical design challenges.

NVIDIA, recognized as one of technology's most desired employers, offers an environment where you can grow into the engineer you aspire to be. The position requires a B.Sc./M.Sc. in Electrical/Computer Engineering with at least 1 year of experience. Ideal candidates will have experience with tools like PrimeTime, PrimePower, RedHawk, and Formality, along with programming skills in Tcl/Perl/Python.

This hybrid position in Yokneam, Israel, offers the opportunity to work with forward-thinking professionals in a company that's transforming industries through AI and accelerated computing. The role combines technical expertise with collaborative teamwork, making it perfect for engineers who thrive on challenges and want to impact the future of technology.

Last updated 3 days ago

Responsibilities For Physical Design Signoff CAD Engineer

  • Develop physical design, STA, Logic eq, Power Integrity flows and methodologies for networking chips and SOCs
  • Work closely with block owners and full Chip STA engineers for quality and timely convergence
  • Develop creative solutions for state of the art physical design problems
  • Develop flow and tool methodologies for timing analysis and closure
  • Work on power and noise analysis, IR-drop, EM and back-end verification across multiple projects

Requirements For Physical Design Signoff CAD Engineer

Python
Linux
  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience)
  • 1+ years of experience
  • Self-motivation and attention to detail
  • Good written, verbal, and presentation skills
  • Ownership and self-learning skills
  • Ability to work autonomously

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