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Senior Chip Design Engineer

NVIDIA is the world leader in accelerated computing, pioneering solutions in AI and digital twins that transform industries.
Tel Aviv-Yafo, IsraelBe'er Sheva, Israel
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Hardware
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Job Description

NVIDIA, the world leader in accelerated computing, is seeking an exceptional Senior Chip Design Engineer to join their Networking Silicon engineering team. This role offers an opportunity to work on cutting-edge high-speed communication devices that deliver industry-leading throughput and latency performance. Based in either Tel Aviv or Beer Sheva, Israel, you'll be part of the accelerators IP group, focusing on RiscV platform unit and cache coherence IP development.

The position involves sophisticated chip design work, requiring expertise in RTL design using Verilog/SystemVerilog, with a strong focus on power optimization, area efficiency, and performance enhancement. You'll be working on microarchitecture and design aspects of chip development, collaborating with firmware teams and other groups globally to create innovative solutions.

This is an excellent opportunity for experienced engineers who want to make a significant impact in a technology-focused company that's transforming industries through AI and digital twins. The role combines technical challenges with the opportunity to work on groundbreaking projects in a professional, growing environment. NVIDIA's position as an industry leader in accelerated computing makes this an ideal role for those looking to advance their careers in chip design while working on technologies that are shaping the future of computing.

The ideal candidate will bring at least 5 years of RTL design experience, a strong educational background in engineering, and excellent English communication skills. Experience with cache coherence protocols, particularly CHI protocol, would be a significant advantage.

Last updated 3 months ago

Responsibilities For Senior Chip Design Engineer

  • Join accelerators IP group working on RiscV platform unit and cache coherence IP
  • Design chip blocks according to specifications under challenging constraints
  • Work on uarch and design aspects of chip development
  • Work closely with Firmware and other groups around the globe

Requirements For Senior Chip Design Engineer

  • B.Sc. in Electrical Engineering/Communication Engineering/Computer Engineering
  • 5+ years of RTL design experience using Verilog/SystemVerilog
  • High Level of English
  • Experience in CHI protocol or other cache coherence protocols (preferred)