CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
Description For CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
Qualcomm is seeking a CPU STA/Timing Engineer at the Senior Staff or Principal Engineer level for their Bangalore, India office. This role is part of the Hardware Engineering team and focuses on physical design timing analysis and closure for complex SOC designs.
Key responsibilities include:
- Working with microarchitecture, RTL design, CAD, and physical design teams to run and analyze timing, driving timing closure
- Implementing and validating constraints with design and DFT teams
- Running SOC timing at all hierarchies and analyzing results
- Collaborating with RTL/DFT teams to facilitate necessary logic changes
- Providing feedback to block and top-level physical design engineers on key fixes for timing closure
- Creating ECOs from timing runs to aid in timing closure
- Documenting and contributing to timing methodology definition
The ideal candidate will have:
- MS degree in Electrical Engineering with 10 years of practical experience
- Extensive experience with industry-standard timing tools and flows
- Deep knowledge of timing closure for multi-clock domain designs
- Experience with deep submicron process technology nodes
- Expertise in STA on large SOCs with multi-scenario timing closure
- Familiarity with circuit modeling, transistor fundamentals, and worst-case corner selection
- Understanding of synthesis, place & route, and tapeout flows
- Strong communication skills to work effectively across teams
This role offers the opportunity to work on cutting-edge technology at a leading innovator in the mobile and wireless communication industry. Qualcomm provides a collaborative environment where you can contribute to world-changing innovations and breakthrough technologies.
Qualcomm offers comprehensive benefits, including health coverage, wealth-building programs, and resources for personal and professional development. The company is committed to fostering a diverse and inclusive workplace that supports innovation and growth.
Join Qualcomm to unlock your full potential and be part of shaping the future of technology in a dynamic, fast-paced environment.
Responsibilities For CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
- Work with design and DFT teams to understand, implement and validate constraints
- Run SOC timing runs at all hierarchies
- Analyze timing and work with RTL/DFT teams to facilitate logic changes required
- Feedback to block level and top level physical design engineers on key fixes required for timing closure
- Work with CAD team to implement timing infrastructure
- Create ECOs from timing runs to help timing closure
- Document and help with timing methodology definition
Requirements For CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
- MS degree in Electrical Engineering with 10 years of practical experience
- Experience in timing flows with industry standard tools
- Experience in all aspects of timing closure for multi-clock domain designs
- Experience with STA on large SOC with multi-scenario timing closure
- Experience with Timing ECO techniques and implementation
- Knowledge of library cells and optimizations
- Familiar with circuit modeling, transistor fundamentals and worst case corner selection
- Solid understanding industry standard tools for synthesis, place & route and tapeout flows
- Good communication skills
- Knowledge of all aspects of timing including noise, cross-talk and others
- Knowledge of basic SoC architecture and HDL languages like Verilog
Benefits For CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
- World-class health benefit coverage for employees and eligible dependents
- Programs to help build and prepare for a financially secure future
- Self and family resources for emotional/mental strength and resilience
- Wellbeing programs to support employees in living and working well
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
Jobs Related To Qualcomm CPU STA/Timing Engineer- Sr Staff/ Principal Engineer
