Sr Lead Engineer - Peripherals Validation
Description For Sr Lead Engineer - Peripherals Validation
Qualcomm India Private Limited is seeking a Senior Lead Engineer for Peripherals Validation to join their hardware engineering team in Bangalore. This role requires 8-12 years of experience in ASIC IP cores design and offers an opportunity to work on cutting-edge technology.
The position demands expertise in AMBA protocols, SoC architecture, and low-power design. You'll be responsible for leading a small design team, working on pre/post Silicon debug with verification teams, and handling complex RTL designs. Strong knowledge of ASIC development tools and timing closure is essential.
The ideal candidate should have a Bachelor's or Master's in Electrical Engineering, with demonstrated experience in multi-clock designs and asynchronous interfaces. You'll need excellent problem-solving abilities and strong communication skills to collaborate effectively across teams.
Qualcomm offers comprehensive benefits including world-class health coverage, financial planning support, and continuous learning opportunities. The company's commitment to innovation and technology leadership makes this an exciting opportunity for someone looking to work with industry experts and contribute to groundbreaking developments in semiconductor technology.
This role provides excellent career growth potential, access to mentorship programs, and the chance to work on challenging projects that impact global wireless technology. Join Qualcomm to be part of a team that's shaping the future of connectivity and computing technology.
Responsibilities For Sr Lead Engineer - Peripherals Validation
- Work closely with SoC verification and validation teams for pre/post Silicon debug
- Lead a small design team
- Develop RTL design from high level specifications
- Handle timing closure and constraint development
Requirements For Sr Lead Engineer - Peripherals Validation
- Bachelor's or Master's degree in Electrical Engineering
- 8-12 years of work experience in ASIC IP cores design
- Knowledge of AMBA protocols - AXI, AHB, APB
- Experience in SoC clocking/reset/debug architecture
- Hands on experience in Low power design
- Experience in Multi Clock designs and Asynchronous interface
- Experience with ASIC development tools (Lint, CDC, Design compiler, Primetime)
- Strong experience in micro architecting RTL design
- Excellent problem solving and communication skills
- Self-driven with ability to work with minimum supervision
Benefits For Sr Lead Engineer - Peripherals Validation
- World-class health coverage for employees and dependents
- Financial planning and future security programs
- Emotional/mental wellbeing support
- Work-life balance programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
