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STA/Timing Engineer

Qualcomm is a world leader in wireless technology innovation.
Backend
Mid-Level Software Engineer
In-Person
5+ years of experience
AI
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Description For STA/Timing Engineer

Qualcomm India Private Limited is seeking a skilled STA/Timing Engineer to join their team in Bangalore, Karnataka, India. This role requires 5 to 10 years of experience in hardware engineering, with a focus on Static Timing Analysis (STA) and timing optimization.

As an STA/Timing Engineer, you will be responsible for various aspects of timing analysis and optimization in multi-mode, multi-voltage domain designs. Your duties will include setting up STA flows, performing timing analysis and validation across multiple PVT conditions, and working with tools like Primetime and Tempus for STA flow optimization and Spice to STA correlation.

The ideal candidate should have a strong background in STA timing analysis basics, AOCV/POCV concepts, and experience with ASIC back-end design flows. You should be proficient in scripting languages such as TCL, Perl, and Awk, and have knowledge of Spice simulation tools like Hspice and FineSim.

This role offers an exciting opportunity to work on cutting-edge hardware designs and contribute to Qualcomm's innovative technologies. You'll be part of a collaborative team environment where your expertise in timing analysis and optimization will play a crucial role in ensuring the performance and reliability of complex semiconductor designs.

Qualcomm offers a comprehensive benefits package and a supportive work environment that encourages professional growth and innovation. Join us in pushing the boundaries of technology and shaping the future of mobile and wireless communications.

If you're passionate about hardware engineering, have a strong background in STA and timing analysis, and are ready to take on challenging projects in a dynamic industry, we encourage you to apply for this STA/Timing Engineer position at Qualcomm India Private Limited.

Last updated 8 months ago

Responsibilities For STA/Timing Engineer

  • STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
  • Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
  • Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation
  • Evaluate multiple timing methodologies/tools on different designs and technology nodes
  • Work on automation scripts within STA/PD tools for methodology development
  • Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
  • Experience in design automation using TCL/Perl/Python
  • Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus
  • Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo

Requirements For STA/Timing Engineer

Java
Python
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience
  • Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
  • Hands-on experience with STA tools - Prime-time, Tempus
  • In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling
  • Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
  • Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation
  • Proficient is scripting languages – TCL, Perl, Awk
  • Basic knowledge of device physics

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