Lead Memory Controller Architect/uArch (Principal Engineer)
Description For Lead Memory Controller Architect/uArch (Principal Engineer)
Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are seeking a Lead Memory Controller Architect/uArch to join their System IP team. This role offers an exciting opportunity to drive the design and development of advanced memory controllers for cutting-edge technologies.
As a Principal Engineer, you'll have end-to-end ownership of memory-controller architecture, including microarchitecture, RTL design, and performance/power optimization. You'll work with various teams to develop innovative memory technologies for Samsung's next-generation products, from mobile to automotive applications.
The System IP team develops proprietary coherent interconnect and memory controllers deployed in high-volume products. They focus on delivering system modeling capability based on optimization and use-case-driven analysis, enabling world-class memory subsystems. The team's work directly influences product roadmaps for market-leading system IP solutions.
The position offers a competitive base salary range of $216,521 to $359,527, along with comprehensive benefits including medical, dental, vision, 401(k), free onsite lunch, and more. You'll be part of a talented team with diverse backgrounds, working in a collaborative environment that encourages innovation and professional growth.
This role requires deep expertise in memory technologies, strong engineering fundamentals, and excellent collaboration skills. You'll be at the forefront of memory technology development, working with cutting-edge technologies like LPDDR5/6, PIM, and beyond. The position offers opportunities to shape the future of memory technology while working for a global leader in semiconductor technology.
Samsung provides a supportive environment for professional growth, with benefits including tuition assistance, wellness programs, and opportunities for bonus compensation. The role is based in either Austin, TX or San Jose, CA, requiring on-site presence to facilitate close collaboration with cross-functional teams.
Responsibilities For Lead Memory Controller Architect/uArch (Principal Engineer)
- Drive design and development of advanced memory controller for cutting-edge technologies
- End-to-end ownership for memory-controller architecture
- Lead microarchitecture development and RTL design
- Collaborate with cross-functional teams
- Ensure design excellence using various tools and methodologies
- Meet performance, power, and area (PPA) targets
- Validate design quality and identify improvements
- Support timing debug and closure
- Adhere to JEDEC standards
Requirements For Lead Memory Controller Architect/uArch (Principal Engineer)
- 20+ years of experience with Bachelor's Degree or 18+ with Master's or 16+ with PhD in Computer Science/Engineering
- Proven experience in memory controller micro-architecture and RTL design
- Deep expertise in memory technologies (LPDDR4/5/6, PIM, DDR, GDDR, HBM)
- Strong knowledge of JEDEC memory standards and DDR PHY
- Expertise in Verilog and ASIC design flow
- Proficiency in scripting languages (Perl, Python)
- Strong communication and collaboration skills
- Familiarity with interface protocols (AMBA, AXI, ACE)
- Knowledge of AES, ECC, and RAS features
Benefits For Lead Memory Controller Architect/uArch (Principal Engineer)
- Free onsite lunch
- Employee purchase program
- Tuition assistance
- Student loan program
- Wellness incentives
- Life insurance
- MBO bonus compensation
- Long term incentive plan
- Relocation Benefits
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