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Cache RTL Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.
$100,000 - $500,000
Embedded
Senior Software Engineer
Hybrid
8+ years of experience
AI
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Description For Cache RTL Design Engineer

Tenstorrent is at the forefront of AI technology, revolutionizing the industry with cutting-edge solutions that redefine performance, usability, and cost-effectiveness. As AI reshapes the computing landscape, Tenstorrent recognizes the need for unified innovations across software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists has developed a high-performance RISC-V CPU from the ground up, driven by a shared passion for AI and a commitment to building the best AI platform possible.

We are seeking an experienced Cache RTL Design Engineer to join our innovative team as a technical expert. In this role, you will be instrumental in developing and implementing the industry's highest performance and most energy-efficient cache and fabric designs. As a key contributor to Tenstorrent's next generation of cores and caches, you'll need to blend creativity with innovation and possess excellent communication skills.

Key responsibilities include:

  • RTL coding in Verilog using industry tools and open-source infrastructure
  • Microarchitecture, design, and development of processor L2 and LLC for high-performance computing systems
  • Designing and micro-architecting caches based on capacity, latency, bandwidth, and RAS requirements
  • Collaborating with cross-functional teams to optimize designs and meet project goals
  • Implementing innovative techniques to improve power, performance, and area of designs
  • Debugging RTL/logic issues across various hierarchies in pre-silicon and post-silicon environments

We're looking for candidates with:

  • BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
  • Expertise in Cache, Multi-processor coherency microarchitecture, and CHI protocol
  • Strong background in computer architecture, system components, networks, and fabrics
  • Proficiency in hardware description languages and simulators
  • Experience with industry-standard ISAs (ARM, RISC-V, or X86)

Join Tenstorrent and be part of a team that values collaboration, curiosity, and a commitment to solving hard problems. We offer competitive compensation and benefits, with engineer salaries ranging from $100k to $500k. If you're passionate about pushing the boundaries of AI technology and want to contribute to the next generation of computing solutions, we want to hear from you!

Last updated 8 months ago

Responsibilities For Cache RTL Design Engineer

  • RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
  • Play a key role in the microarchitecture, design and development of processor L2 and LLC for high-performance computing systems
  • Design and micro architect Caches as driven by capacity, latency, bandwidth, and RAS requirements
  • Drive trade-offs for your logic by working closely with performance, DV and physical design engineers
  • Deploy innovative techniques for improving power, performance and area of the design
  • Debug RTL/logic issues across various hierarchies in both pre-silicon and post-silicon environment

Requirements For Cache RTL Design Engineer

  • BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
  • Experience in Cache, Multi-processor coherency microarchitecture, CHI protocol
  • Experience with computer architecture/system components/network/fabrics
  • Expertise in logic design
  • Strong experience with hardware description languages (Verilog, VHDL) and simulators
  • Experience in microarchitecture definition and specification development
  • Prior experience in industry standard ISAs – ARM, RISC-V, or X86
  • Strong problem solving and debug skills

Benefits For Cache RTL Design Engineer

  • Competitive compensation package
  • Benefits

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