After introducing each other, the interview began with many questions regarding my experiences, computer architecture, and memory coherence and shared memory. The communication was quite good; I would say it was very friendly.

Topics covered included pipeline processor architecture, hazards, shared memory problems, and cache issues. Repeated words in SystemVerilog were also addressed.

I initially answered how to do it in Python, but the interviewer insisted on using C or SystemVerilog.

In the last question, I was asked why I chose design verification.

The whole procedure lasted about 53 minutes, which I would describe as quite tense.

I did not answer the question about memory coherence or about deleting repeated words in C. I feel I did not perform well on these.

Hoping this could help others prepare for job interviews and the questions that might arise.