There were at least 5 interviewers. Some asked about SystemVerilog verification questions, while others inquired about Verilog design. Some firmware engineers were presented with C coding problems. It was quite intensive.
Write down some SystemVerilog constraints.
The following metrics were computed from 1 interview experience for the Broadcom Design Verification Engineer role in San Jose, California.
Broadcom's interview process for their Design Verification Engineer roles in San Jose, California is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Broadcom's Design Verification Engineer interview process in San Jose, California.