They showed PPT on STA. After online test, 25 ppl were shortlisted. There were 3 rounds of interview. Round 1 was to test the basics of digital electronics, CMOS VLSI design, DSA. Round 2 was resume based. Round 3 was HR round.
Draw NAND and NOR implementation using CMOS.
The following metrics were computed from 8 interview experiences for the Cadence Design Systems Applications Engineer role in Bengaluru, India.
Cadence Design Systems's interview process for their Applications Engineer roles in Bengaluru, India is very selective, failing most engineers who go through it.
Candidates reported having very good feelings for Cadence Design Systems's Applications Engineer interview process in Bengaluru, India.