1 hr written test, test involves writing solution of problems. Question were average level but time was very less. There were 3 sections of papers,
This followed by 2 technical round and 1 HR round. 5 students were selected for HR round, but finally company didn't select even single candidate.
Design IIR filter, how to solve overflow issue?
Given a bit vector, swap its adjacent bits eg. 1110011000 =>1101100100
Sampling, and how it affects freq spectrum
The following metrics were computed from 1 interview experience for the Cadence Design Systems DSP Engineer role in Bengaluru, India.
Cadence Design Systems's interview process for their DSP Engineer roles in Bengaluru, India is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Cadence Design Systems's DSP Engineer interview process in Bengaluru, India.