2 rounds of interview one round is completely on Verilog and Digital design questions. Another round is on logic puzzles. Logic puzzles is based on the coins question, 100 prisoners questions
Write Verilog code for asynchronous FIFO, Verilog code for FSM.
The following metrics were computed from 1 interview experience for the Cadence Design Systems Formal Verification Engineer role in India.
Cadence Design Systems's interview process for their Formal Verification Engineer roles in India is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Cadence Design Systems's Formal Verification Engineer interview process in India.