The interview process at Cadence consisted of three rounds:

Resume Screening Round Candidates were required to have a CGPA of 8+ to qualify for the next round. Technical Test : This round consisted of two parts: Part 1: A 1-hour exam with Aptitude(Moderate-level) and Digital Electronics(Moderate-Hard level) questions. Part 2: A 2-hour exam covering topics such as Digital Signal Processing (DSP)(Moderate-Hard Level), C programming(Easy}, Verilog (Easy), and Digital Design (Hard level). Interview Round Successful candidates from the previous rounds were invited for the final interview round. The entire process was rigorous and designed to assess the candidates' technical skills, problem-solving abilities, and knowledge of relevant domains. The company seemed to place a strong emphasis on evaluating the candidates' proficiency in various areas related to the job role.

In this round, I was primarily questioned about my projects and C programming concepts. Some of the questions asked were: Array addition of two arrays in C Access modifiers in Java Candidates were required to write the complete code for all their projects mentioned in the resume. For Deep Learning projects, candidates were asked to explain the architecture of YOLOv5, including details like kernel size, reasons for choosing YOLOv5, preprocessing techniques, and their significance. Other questions covered topics like Bluetooth Low Energy (BLE), flash memory of Arduino boards, macros in C, block diagrams of projects, sensors involved, and associated datasheet questions.