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Verification Engineer Interview Experience - Pune, India

June 1, 2019
Neutral ExperienceNo Offer

Process

Interview process involved aptitude test which contained questions on counter circuits and other digital circuits, basic aptitude followed by 3 rounds of technical interview and one HR interview.

The overall process was very smooth and HR is very cooperative.

Questions

The topics covered are basics of digital electronics, bit manipulation questions, Verilog questions, and questions on pipeline.

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Interview Statistics

The following metrics were computed from 3 interview experiences for the Cadence Design Systems Verification Engineer role in Pune, India.

Success Rate

33%
Pass Rate

Cadence Design Systems's interview process for their Verification Engineer roles in Pune, India is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive33%
Neutral33%
Negative33%

Candidates reported having mixed feelings for Cadence Design Systems's Verification Engineer interview process in Pune, India.

Cadence Design Systems Work Experiences