The role offers a healthy work-life balance.
It would be great if stock benefits were offered to lower levels too.
Interview process was really good with good technical questions. I had three interviews and the time in each was between 30 to 60 minutes. It was a good experience.
Interview was scheduled for one day, back-to-back with 5 people. That included my first and second line managers, one peer test engineer, and two SW/FW engineers. The scheduling was clear, I have received prior email with directions and instructions,
Phone interview was scheduled through email, asked basic Verilog question. Then I was called for an onsite. Received offer after 2 days. Important topics: Writing synthesizable code Understanding ASIC flow. Assertions. How do to debug a design.
Interview process was really good with good technical questions. I had three interviews and the time in each was between 30 to 60 minutes. It was a good experience.
Interview was scheduled for one day, back-to-back with 5 people. That included my first and second line managers, one peer test engineer, and two SW/FW engineers. The scheduling was clear, I have received prior email with directions and instructions,
Phone interview was scheduled through email, asked basic Verilog question. Then I was called for an onsite. Received offer after 2 days. Important topics: Writing synthesizable code Understanding ASIC flow. Assertions. How do to debug a design.