The process began with a 45-minute phone interview, covering questions about my projects, the I2C bus, and cache architecture.

The 1:1 interviews consisted of speaking with two engineers before lunch for 45 minutes each. The third engineer joined for lunch, who was the same individual from the phone interview. Following lunch, a fourth engineer conducted a separate interview, and then a fifth and sixth engineer interviewed me together.

All the engineers took extensive notes as I answered questions. The fourth engineer took photos of two 'C' programs I wrote on the whiteboard, stating he would discuss the questions and answers with the team. In fact, the other two engineers also mentioned they would share the Q&A and make a joint decision.

For the position of Network Diagnostics Engineer at Mountain View, CA, the questions were:

• Address Aliasing
• Memory test algorithms
• 'C' static keyword
• 'C' volatile keyword
• ECC circuits detect a memory write and then a read problem. If there is a problem, how does it detect it if there are two writes alone?
• Write a 'C' program to count the number of 1s in a given 32-bit or 64-bit integer.
• Write a 'C' program to turn ON the 655th bit of an input data stream arriving through an input port. Design it as two functions: setBit and clearBit. The engineer took photos of the programs.
• Finally, the fifth engineer (Architect) and the sixth engineer (junior), I was told, arrived together. The sixth engineer was silent the entire time. The fifth engineer asked me to draw a hardware block diagram of my latest project. He then presented a hardware block diagram and stated that this board was not booting and could not be stepped through with a JTAG ICE debugger. He asked how I would troubleshoot this.

Similar boards run without problems with the same version of firmware. How would you troubleshoot this particular board?

At the end of the interview, they walked me to the exit and said they would get back to me, but ultimately declined to make an offer.

Can you draw the HW block diagram of your latest project and explain it?