I had a phone interview and was later called for an onsite interview.

There were multiple positions available in various aspects of ASIC design, from RTL design, DFT, Physical Design, etc.

They tested my basics in each round.

Basic questions on setup, hold time, and special scenarios were given on the board, and I was asked to solve them. For example, what happens if NMOS and PMOS are inverted in an inverter.

Questions covered basics on scan chains and Boundary Scan design (as it was on my course).

Questions on synthesis included basic constraints in DC, such as set_input_delay, set_output_delay, set_max_fanout, and set_clock_latency.

FSM design and clock frequency divider circuits (by2 and by3) were also discussed. Later, they asked about achieving a 50% duty cycle in a frequency divided by 3 circuit.

They asked me to code an up-down counter in Verilog on the whiteboard. I was also asked about parameters and their usage in Verilog.

Questions were asked on synchronizing data signals between different clock domains.

The physical design round was a bit unexpected.

I was asked about the properties of different metal layers: which has higher capacitance and which has higher resistance.

Other basic questions included clock skew and methods to reduce it.

There were also questions on various low-power designs, such as power gating, clock gating, and using low VDD, etc.

I felt the most difficult question was about different metal layers and their properties.