A one-hour presentation on PhD research work, followed by multiple panels of interviews in teams of two over a few days. Most of the questions were around PhD research, followed by some behavioral questions.
What do the band gap states, both deep and tail states, look like in a particular semiconductor material, and what is their distribution profile?
The following metrics were computed from 1 interview experience for the Intel Device Integration Engineer role in Portland, Oregon.
Intel's interview process for their Device Integration Engineer roles in Portland, Oregon is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's Device Integration Engineer interview process in Portland, Oregon.