Taro Logo

Graphics DFx Design and Validation Engineer Interview Experience - Chandler, Arizona

May 1, 2015
Positive ExperienceNo Offer

Process

First Round:

It was a telephonic interview that lasted around 30-45 minutes. The interviewer discussed my project from the resume and later asked some follow-up questions about it. Other questions covered setup time, hold time, the difference between a latch and a flip-flop, and basic digital design concepts.

Following this, I was invited for an on-site interview.

Questions

Gave me a waveform of a state machine and asked me to draw the state machine from the waveform.

Asked me to draw basic digital design circuits, including sequential circuits based on some conditions.

Discussed setup time, hold time, timing equations, skew, and the ASIC design flow with a brief description of each process.

Was this helpful?

Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Graphics DFx Design and Validation Engineer role in Chandler, Arizona.

Success Rate

0%
Pass Rate

Intel's interview process for their Graphics DFx Design and Validation Engineer roles in Chandler, Arizona is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Graphics DFx Design and Validation Engineer interview process in Chandler, Arizona.

Intel Work Experiences