I received an email first, inquiring about my availability for the interview.

As scheduled, I then received a phone call.

The interview lasted for 45 minutes and was for the Graphics Validation Team in Folsom.

I was expecting resume-related questions, as it was the first round, but I was mistaken.

I sent an email to the interviewer a few days after the interview.

He replied, informing me that I had not been selected.

The questions are as follows:

• Difference between validation and verification?
• What is a race condition?
• Difference between a latch and a flip-flop?
• How to design a ROM?
• What is a state machine?
• Cycle-driven and event-driven simulation differences, and which one is better?
• Functional and code coverage differences.
• Blocking and non-blocking assignments in Verilog.
• How to define variables in Verilog?
• $display and $monitor differences.
• Setup and hold time.
• Hold time violation.
• MESI protocol.
• Page table.
• DRAM and SRAM differences, and how to design them.