One round phone interview.
Four rounds of onsite interviews:
Given Verilog code and asked how it would get synthesized.
Implement Linked List - Verification components in a testbench - Modify classic 5-stage pipeline to accommodate SMT
The following metrics were computed from 1 interview experience for the Intel Verification Engineer role in Portland, Oregon.
Intel's interview process for their Verification Engineer roles in Portland, Oregon is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Intel's Verification Engineer interview process in Portland, Oregon.