Good Balance, Low Stock
Good Balance, Low Stock
Good work-life balance and working environment.
Low stock vesting compared to other companies.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
The interview was 4 hours long and took place at the Intel offices in Toronto. I first met the manager, who was young and knowledgeable. He asked about my passions, where I see myself in 5 years, my projects at school, and my experience in previous
Design Verification Engineer
First, there were some technical questions, and two technical leaders came to the interview. The questions were not very hard, including some basic ones. The technical leaders paid more attention to the value the interviewee could supply to the compa
Design Verification Engineer
Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
Toronto, Ontario, CanadaSeptember 1, 2015The interview was 4 hours long and took place at the Intel offices in Toronto. I first met the manager, who was young and knowledgeable. He asked about my passions, where I see myself in 5 years, my projects at school, and my experience in previous
Design Verification Engineer
Xi'an, Shaanxi, ChinaOctober 1, 2010First, there were some technical questions, and two technical leaders came to the interview. The questions were not very hard, including some basic ones. The technical leaders paid more attention to the value the interviewee could supply to the compa
Design Verification Engineer
Haifa, IsraelJanuary 1, 2022Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
