Supportive, But Company's Future Unsure
Supportive, But Company's Future Unsure
A calm and supportive place, with a good pace to develop skills.
The company is in difficulties and may not survive.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours.
Design Verification Engineer
The interview focused mainly on your previous role at Intel. It included some C++ coding questions and questions on cache coherency. There were also questions on opcode flow from core to target. Overall, it was a heavy technical interview.
Design Verification Engineer
Bengaluru, Karnataka, IndiaAugust 1, 2024They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
IndiaJanuary 1, 20222 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours.
Design Verification Engineer
Atlanta, Georgia, United StatesSeptember 1, 2022The interview focused mainly on your previous role at Intel. It included some C++ coding questions and questions on cache coherency. There were also questions on opcode flow from core to target. Overall, it was a heavy technical interview.
