Good benefits, relative job stability, mostly reasonable management, and cool technologies to work on.
Inter-site political in-fighting, increasingly poor HR, and bad top-level decisions put it in danger.
An increasingly lousy yearly review process destroys trust in the company and between peers.
Be honest and direct, as your values say. Don't fall into ageism.
Ask me about Verilog, SystemVerilog, and UVM basics. I can also answer C/C++ problem-solving questions and discuss my resume projects. My focus is on digital design, verification concepts, coding logic, and real-time debugging approaches. I'm partic
It was overall good. It takes place in multiple rounds, with an HR round also. In the technical round, they will ask questions from hardware as well as software. Deep knowledge of C is required.
Fresh Graduate Interview: Ask about basic logic gate and digital system topics. For example, ask about the output of combinations of logic gates (AND, XOR, flip-flops, clock). Inquire whether candidates have experience with Verilog/VHDL code.
Ask me about Verilog, SystemVerilog, and UVM basics. I can also answer C/C++ problem-solving questions and discuss my resume projects. My focus is on digital design, verification concepts, coding logic, and real-time debugging approaches. I'm partic
It was overall good. It takes place in multiple rounds, with an HR round also. In the technical round, they will ask questions from hardware as well as software. Deep knowledge of C is required.
Fresh Graduate Interview: Ask about basic logic gate and digital system topics. For example, ask about the output of combinations of logic gates (AND, XOR, flip-flops, clock). Inquire whether candidates have experience with Verilog/VHDL code.