Had a phone call with manager and later interviewed for multiple positions....
1:1 and group/panel interview was all about the resume and small design questions and comp arch questions.
They were looking for answers but never looked at the approach.....that was really bad....and I was not comfortable with interviewers except for a couple of people
The circuit is a frequency divide-by-3 clock.
The following metrics were computed from 16 interview experiences for the Marvell Technology ASIC Design Engineer role in Santa Clara, California.
Marvell Technology's interview process for their ASIC Design Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in Santa Clara, California.