After the HR phone screen, there was a one-hr technical phone screen...pretty simple one....basic logic design...microarchitecture...Verilog/SystemVerilog questions.
They took about a month to reply and setup an onsite interview...which was 1:1 with around 6-7 people.
All technical...varied from logic design...to microarchitecture...cache...pipelining....FPGA architecture.....C/C++......Unix/Perl.....Verilog/SystemVerilog qs.....pretty tough questions...took another month to reply for the results. I was happy with the technical expertise they have, though the HR communication is quite slow...they kept me waiting for long....
I had virtual memory questions.
The following metrics were computed from 1 interview experience for the Marvell Technology Verification/Validation Engineer role in Chandler, Arizona.
Marvell Technology's interview process for their Verification/Validation Engineer roles in Chandler, Arizona is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Marvell Technology's Verification/Validation Engineer interview process in Chandler, Arizona.