The interviewer asked for an introduction. In 5 minutes, I was asked to code a UVM sequence, sequencer, and driver for a 32-bit RAM, followed by two assertion questions and two constraint questions.
Constraint for 8-bit opcode (SystemVerilog)
Matrix size based on opcode bit index
The following metrics were computed from 1 interview experience for the Meta Design Verification role in Santa Clara, California.
Meta's interview process for their Design Verification roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Meta's Design Verification interview process in Santa Clara, California.