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Design Verification Interview Experience - Santa Clara, California

April 1, 2025
Neutral ExperienceNo Offer

Process

The interviewer asked for an introduction. In 5 minutes, I was asked to code a UVM sequence, sequencer, and driver for a 32-bit RAM, followed by two assertion questions and two constraint questions.

Questions

Constraint for 8-bit opcode (SystemVerilog)

  • Only one bit can be set in the 8-bit opcode (i.e., one-hot encoding).

Matrix size based on opcode bit index

  • Based on which bit is set in the 8-bit opcode, generate a square 2D array (e.g., if bit 4 is set, the matrix is 4x4).

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Interview Statistics

The following metrics were computed from 1 interview experience for the Meta Design Verification role in Santa Clara, California.

Success Rate

0%
Pass Rate

Meta's interview process for their Design Verification roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Meta's Design Verification interview process in Santa Clara, California.

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