The interview was a 45-minute phone call.
Five minutes were allocated for introductions and background explanation.
The remaining time consisted of technical questions covering digital design and coding.
Comfort with Verilog and experience with ASIC design flow were stated requirements.
AND & OR gates from a 2-to-1 MUX.
What happens if a default case is not used in a case statement?
What are CDC and metastability?
Sequence detecting FSM: coding it in Verilog.
ASIC Design Flow steps.
Creating a unique list from a list with repeats.
The following metrics were computed from 61 interview experiences for the Nvidia ASIC Design Engineer role in United States.
Nvidia's interview process for their ASIC Design Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Nvidia's ASIC Design Engineer interview process in United States.