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ASIC Design Engineer Interview Experience - Beaverton, Oregon

October 1, 2013
Positive ExperienceGot Offer

Process

Applied online at myfuture@nvidia.com and hr@nvidia.com.

There was one round of phone screening followed by six rounds onsite. The phone screening lasted an hour.

I received a call for the onsite interview within a week. The interviewers were great, and all questions led to interesting discussions.

They concentrate on your approach rather than the exact right answer and will help you reach the correct solution.

Questions

STA (Static Timing Analysis) Power analysis and optimization Asynchronous FIFO Clock domain crossing Sequential detector FSM Counter Other Verilog problems Synthesis Minor verification questions Comp Arch topics:

  • Out-of-order execution
  • Tomasulo
  • Cache

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Interview Statistics

The following metrics were computed from 1 interview experience for the Nvidia ASIC Design Engineer role in Beaverton, Oregon.

Success Rate

100%
Pass Rate

Nvidia's interview process for their ASIC Design Engineer roles in Beaverton, Oregon is incredibly easy as the vast majority of engineers get an offer after going through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Nvidia's ASIC Design Engineer interview process in Beaverton, Oregon.

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