Three 45-minute phone interviews were conducted.

The first was timing analysis intensive and went into a lot of detail about timing fix techniques. I was really sleep-deprived during this interview, and we spent 20 minutes talking about the pros and cons of upgrading metal layers. I'm not sure how I passed this interview.

The second interview was more compute architecture-focused but ended in more timing analysis questions, some of which were redundant.

The third was with the hiring manager. Half of it was spent discussing potential roles and answering my questions. The other half focused on describing projects and some technical problems, including more redundant timing analysis questions. They really wanted to ensure I knew backend, I guess.

Typical timing problems:

• Fix hold time and setup time violations
• Power saving techniques
• Jitter
• Skew

Some simple computer architecture topics:

• 5-stage pipeline
• Hazards and how to fix them
• Virtual Memory (VM)

HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew, and explain them in detail.