Good projects were given. Nice mentor and manager. Good office.
Not any as of right now.
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a Verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequenc
The first round was an online assessment of 1 hour. The questions asked included hardware and digital design topics, code outputs, technical questions, and logical reasoning. Once shortlisted, the interview lasted about 45 minutes to 1 hour. There w
1 Interview: * 1 question on state machines * 1 river crossing riddle * 1 question on logic design
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a Verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequenc
The first round was an online assessment of 1 hour. The questions asked included hardware and digital design topics, code outputs, technical questions, and logical reasoning. Once shortlisted, the interview lasted about 45 minutes to 1 hour. There w
1 Interview: * 1 question on state machines * 1 river crossing riddle * 1 question on logic design